The present invention relates to a semiconductor device, a high-frequency power amplifying device (high-frequency power amplifying module) and a wireless communication apparatus with the high-frequency power amplifying device built therein. The present invention relates to, for example, a technology effective for application to a cellular telephone of a multiband communication system, which has a plurality of communication functions different in communication frequency band.
An AMPS (Advanced Mobile phone Service) of an analog system, which has heretofore been used and covers the North America all over the land, and a so-called dual mode cellular telephone wherein digital systems such as TDMA (time division multiple access), CDMA (code division multiple access), etc. are built in one cellular phone, have recently been used in a North American cellular market.
On the other hand, a GSM (Global System for Mobile Communication) system and a DCS (Digital Cellular System) system both using a TDMA technology and an FDD (frequency division duplex) technology have been used in Europe and the like.
xe2x80x9cNikkei Electronicsxe2x80x9d issued by Nikkei Business Publications, Inc., the July 26 issue in 1999 [no.748], P140 to P153 has described a dual mode cellular phone wherein a GSM whose use frequency ranges from 800 MHz to 900 MHz, and a PCN (another name for DSC) whose use frequency ranges from 1.7 GHz to 1.8 GHz, are integrated into one. The same reference has described a multi-layered ceramics-device in which passive parts are brought into integration to downsize the whole circuit.
A dualband-oriented RF power module has been described in xe2x80x9cGAINxe2x80x9d, No. 131, 2000.1 issued by the Semiconductor Group of Hitachi, Ltd.
With advanced information communications, a cellular phone has also been more multi-functioned. Therefore, a high-frequency power amplifying device (high-frequency power amplifying module) built in the cellular phone has also been multi-functioned following it. In a high-frequency power amplifying device having a plurality of communication modes (including a communication band) in particular, the number of assembly parts increases as compared with a single communication mode product, and the device increases in size so that the product cost rises.
Therefore, the present inventors have discussed a size reduction in semiconductor chip in which field effect transistors (MOSFET: Metal Oxide Semiconductor Field-Effect Transistor) have been built therein, in order to bring the high-frequency power amplifying device into less size.
FIGS. 16 through 20 are respectively diagrams related to a high-frequency power amplifying device (high-frequency power amplifying module) 20 discussed in advance of the present invention, and a semiconductor chip in which transistors constituting each final amplifying stage have been built. FIG. 19 is an equivalent circuit diagram of the high-frequency power amplifying device, and FIG. 20 is a typical plan view showing a layout of electronic parts on a wiring board (module substrate) 21B in the high-frequency power amplifying device 20, respectively.
The high-frequency power amplifying device is a dualband type high-frequency power amplifying module. As illustrated in the circuit diagram of FIG. 19, the high-frequency power amplifying device has an amplification system P for a PCN (Personal Communications Network) system as a first amplification system, and an amplification system G for a GSM system as a second amplification system. Thus, FIGS. 19 and 20 are shown inclusive of P as in the case of CP1 (condenser) and RP1 (resistor) in the PCN amplification system P, which are of symbols indicative of a capacitance (condenser) and a resistance constituting a rectifying circuit or the like, and G as in the case of CG1 (condenser) and RG1 (resistor) in the GSM amplification system G.
As shown in FIGS. 19 and 20, external electrode terminals of the amplification system P correspond to an input terminal Pin1, an output terminal Pout1 and a source potential Vdd1, whereas external electrode terminals in the amplification system G correspond to an input terminal Pin2, an output terminal Pout2 and a source potential Vdd2. A reference potential (Ground: GND) and a control terminal Vapc are shared. A selection as to whether either the GSM amplification system G or the PCN amplification system P should be operated, is performed under a changeover of a switch SW1. The switch SW1 is changed over according to a signal supplied to a select terminal Vct1. The control terminal Vapc is connected to the switch SW1. A bias signal supplied to the control terminal Vapc serves so as to supply a bias potential to respective transistors of the GSM amplification system G according to the changeover of the switch SW1. Slender square portions in the circuit diagram shown in FIG. 19 show microstrip lines respectively.
The PCN amplification system P and the GSM amplification system G are both provided in a three-stage configuration [first amplifying stage, second amplifying stage and third amplifying stage (final amplifying stage)] wherein transistors are sequentially cascade-connected. Further, the final amplifying stage takes a power combination configuration wherein two transistors are connected in parallel to increase an output. The transistors make use of MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistors).
Thus, the PCN amplification system P takes a configuration wherein a transistor Q1, a transistor Q2 and parallel-connected transistors Q3 and Q4 are sequentially cascade-connected between the input terminal Pin1 and the output terminal Pout1 as the first amplifying stage, second amplifying stage and final amplifying stage respectively, and constitutes a rectifying circuit on the input side, a rectifying circuit on the output side, and a circuit such as a noise filter or the like. Therefore, condensers (CP1 through CP13), bypass condensers (CB1 and CB2), resistors (RP1 through RP4), and an inductor L1 are disposed in respective locations as discrete parts.
Gate electrodes used as control electrode terminals of the transistors Q1 through Q4 are respectively supplied with a signal to be amplified and a bias potential. The bias potential is a signal supplied to the control terminal Vapc as described above. This signal is supplied to the PCN amplification P or the GSM amplification G by being selected by the switch SW1. The switch SW1 is changed over based on the signal supplied to the select terminal Vct1 to thereby perform such a selection. The potentials supplied to the respective gate electrodes are respectively defined according to predetermined bias resistors.
First electrode terminals (drain electrodes) of the transistors Q1 through Q4 are supplied with the source potential Vdd1. An amplified signal is outputted to the first electrode terminal of each transistor. Second electrode terminals (source electrodes) of the respective transistors are respectively supplied with the reference potential (GND).
The GSM amplification system G takes a configuration wherein a transistor Q5, a transistor Q6 and parallel-connected transistors Q7 and Q8 are sequentially cascade-connected between the input terminal Pin2 and the output terminal Pout2 as the first amplifying stage, second amplifying stage and final amplifying stage respectively, and constitutes a rectifying circuit on the input side, a rectifying circuit on the output side, and a circuit such as a noise filter or the like. Therefore, condensers (CG1 through CG13), bypass condensers (CB3 and CB4), resistors (RG1 through RG4), and an inductor L2 are disposed in respective locations as discrete parts.
Gate electrodes used as control electrode terminals of the transistors Q5 through Q8 are respectively supplied with a signal to be amplified and a bias potential. First electrode terminals (drain electrodes) of the transistors Q5 through Q8 are supplied with the source potential Vdd2. An amplified signal is outputted to the first electrode terminal of each transistor. Second electrode terminals (source electrodes) of the respective transistors are respectively supplied with the reference potential (GND).
The transistors Q1, Q2, Q5 and Q6 are monolithically formed in a chip 1. The transistors Q3 and Q4, which constitute the final amplifying stage of the amplification system P, are monolithically formed in a chip 2. The transistors Q6 and Q8, which constitute the final amplifying stage of the amplification system G, are monolithically formed in a chip 3.
The electrodes of the respective chips and wire bonding pads 21D of wirings 21W provided on a main surface of the wiring board 21 are electrically connected to one another by conductive wires 14. Electrodes provided on the lower surfaces of the respective chips are respectively electrically connected to conductive fixed portions continuously connected to wirings when they are fixed to the wiring board 21. Thus, the circuit shown in FIG. 19 is configured. Although not described in particular, passive parts, which constitute condensers, resistors and inductors, etc., result in surface-mountable chip parts. The respective electrodes are electrically connected to their corresponding electrode connecting portions continuously connected to their corresponding wirings, by means of solder.
Meanwhile, the semiconductor device (semiconductor chip) 10 having built therein the transistors constituting the final amplifying stages, has such an electrode layout configuration as shown in FIGS. 16 and 18. FIG. 16 is a typical plan view of the semiconductor device (semiconductor chip) 10 having incorporated therein the transistors constituting the final amplifying stages, FIG. 17 is an equivalent circuit diagram of the semiconductor device, and FIG. 18 is a typical plan view showing electrode patterns for the transistors, respectively. The semiconductor chip 10 constitutes each of the chips 2 and 3 shown in FIGS. 19 and 20. The semiconductor chip 10 shows an example of the chip 3 and will be explained using FIG. 18.
The semiconductor chip 10 is shaped in the form of a rectangle. In the semiconductor chip 10, gate electrode pads 11 are arranged along one long side of the rectangle, drain electrode pads 12 are arranged along the other long side thereof, and a source electrode pad 13 is provided at an intermediate portion of the one long side. In the drawing, the gate electrode pads 11 and the drain electrode pads 12 are respectively arranged eight in a row and divided into two four by four. A resistor R5 is connected between the gate electrode pads 11 divided into the two, and a resistor R6 is connected between the drain electrode pads 12 divided into the two. In the case of the chip 2, the drain electrode pads are arranged six in a row and divided into two three by three.
As shown in FIG. 16, a portion including a source electrode pad 13, and gate electrode pads 11 and drain electrode pads 12 provided on the left side of resistors R5 and R6 constitutes a first transistor portion (FET1), whereas a portion including the source electrode pad 13, and gate electrode pads 11 and drain electrode pads 12 provided on the right side of the resistors R5 and R6 constitutes a second transistor portion (FET2). The FET1 and FET2 constitute the transistors Q3 and Q4 in the chip 2 shown in FIGS. 19 and 20, and constitute transistors Q7 and Q8 in the chip 3 shown in FIGS. 19 and 20.
As shown in FIG. 18, the electrode patterns are brought to a finger pattern structure wherein fingers of respective electrodes engage with one another in a comb-teeth form. Such an electrode pattern configuration results in such a structure as to shorten the fingers in order to avoid a delay in signal""s phase. Thus, as a result of adoption of such a structure as to shorten the fingers while the gate electrode pads and the drain electrode pads are being provided face to face with one another, the semiconductor chip 10 results in a slender structure as shown in FIG. 16. For instance, the size of the semiconductor chip 10 becomes 2 mm long and 1 mm wide.
However, when the semiconductor chip 10 becomes slender in this way, the size of the wiring board on which the semiconductor chip 10 is mounted, also increases and hence the high-frequency power amplifying device is also upsized.
An object of the present invention is to provide a semiconductor device with amplifiers built therein, in which a difference in length-to-width dimension is small.
Another object of the present invention is to provide a downsizable high-frequency power amplifying device.
A further object of the present invention is to provide a wireless communication apparatus capable of being reduced in size.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be explained in brief as follows:
(1) There is provided a semiconductor device, comprising:
a semiconductor substrate; and
transistors formed on the semiconductor substrate,
wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate,
wherein the one or more control electrode terminals are provided, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween,
wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and
wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode terminals constitute a second transistor portion.
The semiconductor device can be rendered close to a square. The first electrode terminals are respectively arranged in a row along a pair of faced sides of the semiconductor substrate, and the control electrode terminals are placed in between both the rows. Each of the semiconductor regions formed on the semiconductor substrate respectively electrically connected to the control electrode terminals and the first electrode terminals and second electrode terminals for the transistors takes a finger structure. The length of each finger becomes less than or equal to 300 xcexcm. The transistors are respectively field effect transistors formed on a silicon substrate. Gate electrode terminals thereof serve as the control electrode terminals, drain electrode terminals thereof serve as the first electrode terminals, and source electrode terminals thereof serve as the second electrode terminals, respectively.
Such a semiconductor device is incorporated as each final amplifying stage of a high-frequency power amplifying device having the following configuration. The high-frequency power amplifying device comprises one or more amplification systems formed on a wiring board, each of which comprising,
an input terminal supplied with a signal to be amplified;
an output terminal;
a control terminal which receives a power control signal therein;
a plurality of amplifying stages sequentially cascade-connected between the input terminal and the output terminal; and
a first power terminal and a second power terminal which respectively supply predetermined potentials to the amplifying stages,
wherein each of the amplifying stages includes control electrode terminals which receive an input signal and the power control signal supplied thereto, first electrode terminals each of which transmits an output signal of the amplifying stage, and second electrode terminals each connected to the second power terminal.
The transistors are provided on the semiconductor substrate in plural form.
The semiconductor device is square and the first electrode terminals are respectively arranged in rows along a pair of faced sides of the semiconductor substrate. Further, the control electrode terminals are located in between both the rows.
Respective semiconductor regions formed on the semiconductor substrate, which are respectively electrically connected to the control electrode terminals and the first electrode terminals and second electrode terminals for the transistors provided in the semiconductor device, serve as a finger structure. Further, the length of each finger of the finger structure is set to less than or equal to 300 xcexcm so as to avoid an increase in signal phase shift.
The first electrode terminals and the control electrode terminals for the transistors of the semiconductor device constitute wire bonding pads to which conductive wires are connectable. Second electrode terminals serving as external electrode terminals are provided on the back surface of the semiconductor substrate. The control electrode terminals serve as a long-extending strip electrode, and one end of the wire is connected to one desired spot of the strip electrode.
The first electrode terminals, control electrode terminals and second electrode terminals constituting the external electrode terminals of the transistors are provided on a main surface of the semiconductor substrate constituting the semiconductor device. Further, these respective electrode terminals serve as protruded electrodes. They are connected to their corresponding wirings on the wiring board via the protruded electrodes.
The first electrode terminals of the first transistor portion employed in the semiconductor device, and the first electrode terminals of the second transistor portion employed therein are respectively electrically connected to one another via a resistor provided on the semiconductor substrate constituting the semiconductor device.
The transistors are respectively field effect transistors formed on a silicon substrate, and gate electrode terminals thereof serve as the control electrode terminals, drain electrode terminals thereof serve as the first electrode terminals, and source electrode terminals thereof serve as the second electrode terminals, respectively.
A first-stage amplifying stage and a second-stage amplifying stage in each the amplification systems are monolithically formed on a single semiconductor chip.
In the high-frequency power amplifying device in which the amplification systems are provided at least two, the respective transistors constituting the respective final amplifying stages in the respective amplification systems are built in a single semiconductor substrate. Wires for connecting the control electrode terminals of the respective transistors and the wirings on the wiring board and wires for connecting the first electrode terminals of the respective transistors and the wirings on the wiring board respectively extend in a direction to intersect one another between the adjacent transistors and between the adjacent wires.
An angle at which both the wires intersect is 30xc2x0 or more.
The semiconductor device is square.
A wireless communication apparatus has the high-frequency power amplifying device referred to above.
The high-frequency power amplifying device is built in a wireless communication apparatus.
According to the means of the above (1), (a) There is provided a structure wherein a plurality of drain electrode pads are disposed along one of the sides of a semiconductor chip with gate electrode pads being interposed therebetween, and a plurality of drain electrode pads are disposed along the other thereof of the semiconductor chip. Therefore, the semiconductor chip can be rendered close to a square. As a result, when the semiconductor chip is built in a high-frequency power amplifying device, a wiring board of the high-frequency power amplifying device can be reduced as compared with the case in which a slender semiconductor chip is incorporated therein, and the high-frequency power amplifying device can be made small-sized. Owing to the size reduction in the high-frequency power amplifying device, a wireless communication apparatus with the high-frequency power amplifying device built therein can be also reduced in size.
(b) Since electrode patterns for transistors are configured as a finger pattern structure, and the length of each finger is set to less than or equal to 300 xcexcm, a phase shift in signal does not increase.